Pracownik Widok v2

Informacje o Pracowniku
dr inż. Rafal Kiełbik +48 42 631 27 22 http://fiona.dmcs.pl/~rkielbik

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Poniedziałek
POi, CTI 301
Praca własna
POi, CTI 301
Wtorek
Seminarium, DMCS A1
Visit. hours, DMCS 29
Praca własna
POi, CTI 302
Środa
Praca własna
POi, lab B
POe, lab B
Czwartek
Visit. hours, DMCS 29
Praca własna
POi, CTI 302

Informacje dla studentów nagłówek

Informacje dla studentów

Widok zawartości stron

CV nagłówek

Curriculum Vitae

CV

He was born in 1974 in Lodz. In 1998 he received the M.Sc. degree from TUL. In the same year he has started a Ph.D. course. In 1999 he spent four months on scholarship in Barcelona. In 2005 he received Ph.D. degree from TUL and in 2006 from UPC in Barcelona. He is interested in programmable devices, hardware description languages and automatic synthesis of electronic devices.

Participation in Research Projects

2009 – present Grant of Polish Ministry of Science and Higher Education 3361/B/T02/2009/36: „Module of Dedicated Computational Cluster for Simulations Based on Dynamic Lattice Liquid Algorithm" (main researcher)
2006 – 2010 European Project (FP6) IST-2006-34632: "PERPLEXUS - Pervasive Computing Framework for Modelling Complex Virtually-Unbounded Systems" (Polish team coordinator)
2006 – 2008 Grant of Polish Ministry of Science and Higher Education 3 T08E 104 29: „Implementation of Dynamic Lattice Liquid Algorithm by Means of Dedicated Microprogrammable Computational Cell" (researcher)
2003 – 2004 Grant of Polish Scientific Research Council 4 T11B 004 24: „High-level Partitioning Algorithm Dedicated to Dynamically Reconfigurable Devices with Multi-context Reconfiguration (main researcher)
2002 – 2005 European Project (FP5) "RECONF2 – Design Methodology and Environment for Dynamic Reconfigurable FPGA" (researcher)
2000 – 2001 Grant of Polish Scientific Research Council 8 T11B 016 19: „Algorithm of Partitioning the Structure Described in VHDL into Two Equivalent Sub-structures" (main researcher)

Papers on international conferences

1. KIEŁBIK R., JABŁOŃSKI G., ŚWIERCZ B., AMROZIK P., "Instructionless processor architecture using dynamically reconfigurable logic", Proceedings of the 17th International Conference "Mixed Design of Integrated Circuits and Systems" MIXDES'2010, Wrocław, Poland 24-26 June 2010, pp. 112-116
2. JUNG J., POLANOWSKI P., PAKULA T., KIELBIK R., NAPIERALSKI A., ULANSKI J., „Hardware implementation of Dynamic Lattice Liquid model as a way of investigation of very complex molecular systems", Proceedings of the 6th Hellenic Conference on Polymers, Patras, Greece, November 2006, pp. 285-286
3. KAFKA L., KIEŁBIK R., MATOUSEK R., MORENO J.M., "VPart: An Automatic Partitioning Tool for Dynamic Reconfiguration", Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA'2005), pp. 263, Monterey, California, USA, February 2005, ISBN 1-59593-029-9
4. KLEPACZKO A., NAPIERALSKI A., KIEŁBIK R., MORENO J.M. „Hardware Implementation of Programmable Neural Networks for CHEMFET Signals Analysis in SEWING Project", An Interdisciplinary Integrative Forum on Nanotechnology, Biotechnology Microtechnology Nanotech 2003 (MSM 2003, ICCN 2003), February 23-27, 2003, San Francisco, California, USA, pp. 115-118, ISBN 0-97284422-0-9
5. KLEPACZKO A., KIEŁBIK R., NAPIERALSKI A., MORENO J.M.: „Hardware Implementation of Programmable MLP Structure on the Triscend SoC Devices", AICM'02 Artificial Intelligence in Control and Management, Łódź, September 25-26, 2002, pp. 23-34,
6. KIEŁBIK R., MORENO J.M., NAPIERALSKI A., JABŁOŃSKI G., SZYMAŃSKI T.: "High-Level Partitioning of Digital Systems Based on Reconfigurable Devices", 12th International Conference, FPL 2002, Montpellier, France, September 2-4, pp. 271-280, (Springer)
7. KLEPACZKO A., NAPIERALSKI A., KIEŁBIK R., MORENO J.M., CABESTANY J.: „Hardware Implementation of Programmable Multi-Layer Perceptron Structure on The Triscent System-on-Chip Devices", Proceedings of the 9th International Conference "Mixed Design of Integrated Circuits and Systems" MIXDES'2002, Wrocław, Poland 20-22 June 2002, pp. 297-302
8. SZYMAŃSKI T., KIEŁBIK R., NAPIERALSKI A.: "Architecture of reprogrammable processor specified for video processing", Proceedings of the VI-th International Conference CADSM 2001, The Experience of Designing and Application of CAD Systems in Microelectronics, 12-17 February 2001, Lviv-Slavsko,Ukraine, pp. 47-48
9. SZYMAŃSKI T., KIEŁBIK R., NAPIERALSKI A.: "SDRAM controller for real time digital image processing systems", Proceedings of the VI-th International Conference CADSM 2001, The Experience of Designing and Application of CAD Systems in Microelectronics, 12-17 February 2001, Lviv-Slavsko,Ukraine, pp. 72-75
10. SZYMAŃSKI T., KIEŁBIK R., NAPIERALSKI A.: "In-system reconfiguring and I2C controlling of FPGA based applications", Proceedings of the VI-th International Conference CADSM 2001, The Experience of Designing and Application of CAD Systems in Microelectronics, 12-17 February 2001, Lviv-Slavsko,Ukraine, pp. 230-231
11. RADECKI A, GOSŁAWSKI R., MORENO J.M. , NAPIERALSKI A., KIELBIK R., "Development of a Remote Simulation Environment Based on FIPSOC Programmable Devices", 8th International Conference Mixed Design of Integrated Circuits and Systems MIXDES'2001, June 21-23, 2001, Zakopane, Poland, pp. 329-332
12. GOSŁAWSKI R., RADECKI A, MORENO J.M. , NAPIERALSKI A., KIELBIK R. , SZYMAŃSKI T.: "Design of Distributed Arithmetic FIR Modules for the FIPSOC Programmable Devices", 8th International Conference Mixed Design of Integrated Circuits and Systems MIXDES'2001, June 21-23, 2001, Zakopane, Poland, pp. 483-486
13. MORENO J.M., NAPIERALSKI A., KIEŁBIK R., LACADENA I., INSENSER J.M.: "FIPSOC – New Concept of Programmable Devices", 3rd DDECS Workshop Smolenice castle, Slovakia, April 5-7, 2000, pp. 154-160.
14. KIEŁBIK R., MORENO J.M., NAPIERALSKI A., SZYMAŃSKI T,: "High-Level Partitoning for Dynamically Reconfigurable Logic", In Proceeding 7th international workshop conference: " Mixed Design of Integrated Circuit and Systems", MIXDES'2000, Gdynia, Poland, 15-17 June 2000, pp. 171-174
15. MORENO J.M., MADRENAS J., CABESTANY J., CANTO E., KIEŁBIK R., FAURA J., INSENSER J.M.: „Realization of Self-Repairing and Evolvable Hardware Structures by Means of Implicit Self-Configuration", The First NASA/DoD Workshop on Evolvable Hardware, July 19-21,1999, Pasadena, California, pp. 182-187

Awards

2005 – award of Faculty Council for PhD dissertation entitled: "Efficient Methods Of Resource Management In Re-Programmable Systems"