Widok zawartości stron

  1. Algorithm for face tracking in video sequence dedicated for biometric authentication systems.
    Duration: 4 months

    http://www.biometrics.dmcs.pl/
    contact: Wojciech Sankowski, e-mail: wsan@dmcs.pl
     
  2. Acquisition and real-time preprocessing of images using multicore DSP processors.
    
Abstract: The main of the work is to design and implement system based on C6678 digital signal multicore processor connected with 1GigE camera able to grab and preprocess frames. For this purpose one can use TMS320C6678 development board, so no electronic design is required. The proposed system is a part of biometric project related to recognition at-a-distance and on-the-move.

    contact: Kamil Grabowski, e-mail:kgrabowski@dmcs.pl

    web: www.biometrics.dmcs.pl
     
  3. Optimizations of code generation in an OpenACC compiler.
    Abstract: Application of improvements of code generation algorithm in an existing OpenACC compiler developed at Department of Microelectronics and Computer Science.
    
Duration: 12 Months
    Web link: www.dmcs.pl

    Area of study: computer science

    Title we issue: Master of Computer Science
    contact: Grzegorz Jabłoński, e-mail: gwj@dmcs.pl
     
  4. Analysis and visualization of data from photovotaic system.
    Abstract: A photovoltaic system delivers electrical energy into utility grid. All its operation parameters are recorded by a monitoring system for further scientific analysis. The large size of collected data make them difficult to process, especially if some custom calculations are needed. The purpose of this thesis is to create a software to deal with large data files, use robust and mature software technologies, calculate and visualise selected parameters and make the functional user interface, possibly web-based.
    Field: Computer Science.
    Duration: 1 semester
    English Level: CEFR=B2, ESOL=FCE, IELTS=5.0, TOEFL=500 or equivalent.
    Study Level Completed: B.Sc.
    contact : Witold Marańda, e-mail: maranda@dmcs.p.lodz.pl
     
  5. Back-annotated simulations of multi-context dynamically reconfigurable circuits.
    Short description:The goal of this thesis is to develop testbenches in VHDL (Very High Speed Integrated Circuits Hardware Description Language) for reliable timing and functional verification of multi-context dynamically reconfigurable circuits. These tests will be based on back-annotated simulations.
    English level: fluent
    Study level completed: bachelor of science in electronic engineering.
    contact: Piotr Amrozik, e-mail:pamrozik@dmcs.pl
     
  6. Electronic fairs implemented in the form of an Internet platform.
    Description: Web application with functionality similar to advanced internet shop applied to the area of  electronic fairs.
    English level:  B2 (First Certificate or similar)
    contact: Bartosz Sakowicz, e-mail:sakowicz@dmcs.pl
     
  7. Encrypted instant voice messaging system.
    Description: Real-time voice messaging system working on encrypted protocol such as SSL
    English level:  B2 (First Certificate or similar)
    contact: Bartosz Sakowicz, e-mail:sakowicz@dmcs.pl
     
  8. Customizable robot collecting data from Internet forums.
    Description: Network application able to search through configured list of forums for particular information
    English level:  B2 (First Certificate or similar)
    contact: Bartosz Sakowicz, e-mail:sakowicz@dmcs.pl
     
  9. Business card exchange system based on Android and IOS.
    Description:  IOS and Android application which will be able to communicate, when two phones are in close range and to exchange data between owners.
    English level:  B2 (First Certificate or similar)
    contact: Bartosz Sakowicz, e-mail:sakowicz@dmcs.pl
     
  10. The image processing system for On-tree Fruit Recognition
    Description: The implementation of on-tree fruit image system recognition (for more see Jun Zhao, Joel Tow and Jayantha Katupitiya(2005)
    English level:  B2 (First Certificate or similar)
    contact :Mariusz Zubert, e-mail:mariuszz@dmcs.p.lodz.pl
     
  11. Translation of Coloured Petri Nets into high-level programming language.
    
Abstract: The goal of the thesis is to develop a methodology for converting formal models of hardware or software systems, made in terms of Coloured Petri Nets into one of known high-level programming languages (C/C++, Java). The language is to be selected by applicant.
    Duration: 12 months

    Requirements: Bachelor of Science in Computer Science received, good programming skills in one of the languages mentioned in abstract, at least communicative English skills.
    
contact: Maciej Piotrowicz, e-mail:piotrowi@dmcs.p.lodz.pl.
     
  12. Design of integrated circuit in high-voltage silicon technology with special consideration of power density dissipation.
    Brief description: Design of integrated circuit which operates with high-voltage. Electrical schemes and layout design in cadence environment ends by final layout preparation for manufacturing. 
Requirements: 
- English level - communicative with technical words knowledge 
- Study level completed: Electronic Eng., Integrated Circuits
    contact: Michał Szermer,e-mail: szermer@dmcs.p.lodz.pl
     
  13. Analysis of software power modelling tools for modern processors.
    
Abstract: Student will first perfom a survey of existing power modelling tools for modern processors. The survey will consist on comparing these solutions in terms of accuracy, flexibility and speed. Student will also run power simulations using these tools and describe the obtained results.
    Requirements: Basic knowledge of processor architecture and programming in C, good English
    
Title issued: M.Sc. in electronics
    Duration: 1 year
    Contact: Piotr Zajac, e-mail: pzajac@dmcs.pl
     
  14. FEM simulations of thermal phenomena in multicore processors.
    Abstract: This work concerns thermal phenomena in today's and future multicore processors. Due to miniaturization and increasing the number of cores, thermal dependencies between cores become more significant. The cooling of such processors become more difficult. The aim of this work is to simulate multicore processors using FEM simulation software in order to detect and estimate the potential thermal problems.
    Title issued: M.Sc. in electronics
    Duration: 1 year
    Requirements: English level: communicative
    Skills: basic knowledge about thermal phenomena and computer architecture
    contact :Cezary Maj, e-mail:cmaj@dmcs.pl
     
  15. Optimization of core floorplan in multicore processors.
    Abstract: This work concerns thermal dependencies between cores in today's and future multicore processors. Due to miniaturization and increasing the number of cores the local temperature is highly dependent on arrangement of cores and their internal units. The aim of this work is to simulate multicore processors using FEM simulation software in order to find the optimal floorplan from the thermal point of view.
    Duration: 1 year M.Sc. in electronics
    Requirements: English level: communicative
    Skills: basic knowledge about thermal phenomena and computer architecture
    contact : Cezary Maj, e-mail: cmaj@dmcs.pl
     
  16. Fast Implementation of Bayesian Networks with Learning Algorithm.
    Abstract: The goal is to develop implementation of Bayesian networks, together with selected algorithm for parameter learning, that will be competitive -- in terms of computation speed -- with existing solutions. The solution should employ possibilities offered by modern PC hardware: SIMD processing, multicore/multiprocessor architectures, GPU computations.
    English level: Intermediate
    Duration: 12 months
    Title issued: MSc
    contact : Wojciech Tylman, e-mail: tyl@dmcs.p.lodz.pl
    http://www.dmcs.pl/web/tyl/strona-pracownika
     
  17. Application of video processing algorithms for mobile platforms
    Abstract: Application of dedicated video processing algorithms for mobile platforms i.e. iOS, Android, Windows Phone. Developing of novel solutions and adaptation of current ones for given problems.
    Field: Computer Science
    contact : Przemysław Sękalski, e-mail: sekalski@dmcs.pl
     
  18. FPGA support for video processing.
    Abstract: Application of dedicated video processing algorithms in FPGA-based devices (i.e. Zynq platform). Developing of novel solutions and adaptation of current ones for given problems.
    Field: Computer Science/Electronics
    contact: Przemysław Sękalski, e-mail: sekalski@dmcs.pl
     
  19. ARM support for video processing
    Abstract: Application of dedicated video processing algorithms in ARM-based devices (i.e. Zynq platform). Developing of novel solutions and adaptation of current ones for given problems.
    Field: Computer Science/Electronics
    contact person: Przemysław Sękalski, e-mail: sekalski@dmcs.pl
     
  20. High Input Impedance Integrated High-Voltage Buffers and Amplifiers
    
Small abstract :The work is to be focused on analysis, design and possible improvements of high-voltage unity-gain buffers and amplifiers. These types of function blocks tend to be difficult in implementation into integrated circuits. 
Problems are very pronounced if very high input impedance and no input DC path is required. The known circuit solution should be analyzed and possible improvements or new structures should be proposed and analyzed.
    Study completed: BSc, or during MSc course
    Duration: 12 months
    
English level: communicative

    contact: Mariusz Jankowski, e-mail: jankowsk@dmcs.p.lodz.pl
     
  21. Overview of existing testing frameworks for C++ application with special consideration of usage in DOOCS servers environment.
    Short abstract: Development of control software for High Energy Physics (HEP) systems is very important part of preparation of new accelerator techniques and experiments. Reliability and availability of the software components defines correctness of achieved results therefore failure may have very serious consequences. In the framework of this master thesis, overview of existing testing frameworks for C++ applications must be prepared with consideration of possible usage of selected tools to increase reliability and availability of produced accelerator control systems. Possible connections of different techniques or development of new one are also possible.   
    Duration: 12 months
    Research group: DESY Collaboration Group in Department of Microelectronic and Computer Science
    Requirements: computer science, good C++ programming language knowledge
    Contact : Adam Piotrowski, e-mail: komam@dmcs.pl
     
  22. Software testing framework for hardware components of uTCA-based LLRF control system.
    Short abstract: Control system for High Energy Physics (HEP) experiments is composed of control applications and appropriate hardware components. Reliability and availability of both parts of system defines correctness of achieved results therefore failure may have very serious consequences. Appropriate testing procedure to check correctness of embedded system used in HEP experiments is critical part of development of new systems. In the framework of this master thesis new software testing framework for hardware components of uTCA-based Low Level RF control system for FLASH will be developed.
    Duration: 12 months
    Research group: DESY Collaboration Group in Department of Microelectronic and Computer Science.
    Requirements: computer science, good C++ programming language knowledge
    Contact : Adam Piotrowski, e-mail: komam@dmcs.pl
     
  23. Development of Algorithms for Real-time Image Acquisition System. 

    Abstract: High-resolution, fast digital cameras are used for plasma evaluation in modern Physics. The image acquired from the camera is buffered and transmitted for further processing. Smart and efficient algorithms need to be developed for image processing using CPU and GPU under Linux.
    
Good knowledge of C/C++ is required.
    
Duration: (12 Months)

    contact: Dariusz Makowski, e-mail: dmakow@dmcs.pl
     
  24. Development of Algorithms for Image Processing using FPGA. 


    Abstract: High-resolution, fast digital cameras are used for plasma evaluation in modern Physics. The image acquired from the camera is buffered and transmitted for further processing. Signal from digital cameras can be used for triggering interlock in critical situations. Low latency, efficient algorithms need to be developed for image processing using FPGA devices.
    
Good knowledge of FPGA and VHDL is required.
    
Duration: (12 Months)

    contact: Dariusz Makowski, e-mail: dmakow@dmcs.pl
     
  25. Development of FPGA Firmware for Timing Module. 


    Abstract: Modern Data Acquisition Systems (DAQs) require precision timing with resolution better than 50 ns. DMCS has developed a dedicated FPGA-based timing board for DAQs using IEEE1588 protocol. A suitable firmware for FPGA device and software processor was already developed. The software and firmware require further improvements to meet the 50 ns requirements.
    
Good knowledge of FPGA and VHDL is required. 
    
Duration: (12 Months)

    contact: Dariusz Makowski, e-mail: dmakow@dmcs.pl
     
  26. Development of Linux Driver and Software for Timing Module.
    

Abstract: Modern Data Acquisition Systems (DAQs) require precision timing with resolution better than 50 ns. DMCS has developed a dedicated FPGA-based timing board for DAQs using IEEE1588 protocol. A firmware for FPGA device and software processor was already developed. A suitable Linux driver and high-level software need to be develop to control the board.
    Good knowledge of C/C++ is required. 

    Duration: (12 Months)

    contact: Dariusz Makowski, e-mail:dmakow@dmcs.pl
     
  27. Measurement of electric signal parameters in electronic converters using the chirp Z-transform. 

    Abstract: Most power converter parameter definitions (e.g. efficiency, power factor) involve averaging over fundamental period. Analysis in the frequency domain based on Discrete Fourier Transform is more efficient but also requires precise knowledge of the fundamental frequency. The aim of the project is to implement the chirp Z-transform in a microcontroller and to use it to process electrical signals (current and voltage waveforms) typical for switched-mode power electronic converters. The chirp Z-transform may be considered a generalisation of DFT. It provides a greater frequency resolution, which will enable not only calculating operating parameters (harmonic distortion, active power etc.) but also determining the fundamental frequency automatically. 

    Requirements: BSc in electronic engineering; practice in microcontroller programming, understanding of DFT topics, skills in electronic circuit design and assembly;
    English level sufficient to understand university textbooks, short scientific texts, component documentation and application notes 

    Title issued: MSc in Electronics and Telecommunications 

    
contact: Prof. Andrzej Napieralski /dr  Łukasz Starzak, e-mail: starzak@dmcs.p.lodz.pl
    Web-link: http://dmcs.p.lodz.pl
     
  28. Time-frequency analysis of acoustic signals.
    The topic is focused on a project and realization of computer software dedicated to acoustic signal analysis including speech processes. Proposed algorithm give us a possibility to extract feature vectors of audio signals. Student should has a basic knowledge of time-domain and frequency-domain analysis of analogue and digital signals. The knowledge of Java programming is also necessary.
    Duration: 12 months
    contact: Zygmunt Ciota, e-mail: ciota@dmcs.pl,
    web: www.dmcs.pl
     
  29. Efficient data streaming over 10Gbps Ethernet.
    The aim of the topic is to propose, implement and test reliable data transfer protocol suitable for data transfers through 10Gps connection with high performance, low CPU load. The scope of the work should include jumbo-frames, DMA technique for zero-copy approach in data transfers etc. The implementation should be done in C++ object oriented programming.
    contact: Mariusz Orlikowski, e-mail: mariuszo@dmcs.p.lodz.pl
     
  30. Thermal characterisation of electronic system components.
    contact: Marcin Janicki, e-mail: janicki@dmcs.pl
     
  31. A modbus master simulator.
    Abstract: A computer application designed to help developers of Modbus slave devices or others that want to test and simulate the Modbus protocol. Java implementation with jamod library, Hibernate and PostgreSQL. A slave registers configuration shoud be stored in a database. The data should be obtained from the slave regardless of the format of the data stored in the registers.
    Supported protocol variants:
    -Modbus RTU
    -Modbus RTU Over TCP/IP
    -Modbus TCP/IP (optional)

    Supported modbus functions:
    03: Read holding register
    contact: Sławomir Wróblewski, e-mail: swroble@dmcs.p.lodz.pl