Projekt:

Circuit designed by Jean Louis Noullet from PFMT (Pôle de Formation en Micro-électronique de Toulouse).
This work has been supervised by prof. Adrzej Napieralski - Head of Department of Microelectronics and Computer Science of Technical University of Lodz.

Chip Details:

Process: Mietec 2.4um CMOS
Area: ~4.5 sqmm
Production: 10 specimen, France

Projekt:

Circuit designed by Jean Louis Noullet from PFMT (Pôle de Formation en Micro-électronique de Toulouse).
This work has been supervised by prof. Adrzej Napieralski - Head of Department of Microelectronics and Computer Science of Technical University of Lodz.

Chip Details:

Process: Mietec 2.4um CMOS
Area: 7 sqmm
Production: 10 specimen, France

Projekt:

Circuit designed by Jean Louis Noullet from PFMT (Pôle de Formation en Micro-électronique de Toulouse).
This work has been supervised by prof. Adrzej Napieralski - Head of Department of Microelectronics and Computer Science of Technical University of Lodz.

Chip Details:

Process: Mietec 2.4um CMOS
Area: 5 sqmm
Production: 10 specimen, France

Projekt:

Joint European Project JEP - 4343, "Education of computer aided design of modern VLSI circuits": 1992-1995.

Chip Details:

Process: Mietec 2.4um CMOS
Area: -
Production: 10 specimen, 1993

Projekt:

Joint European Project JEP - 4343, "Education of computer aided design of modern VLSI circuits": 1992-1995.
Scientific grant entitled: "Integration of temperature sensors in silicon semiconductor structures".

Chip Details:

Process: Mietec 2.4um CMOS
Area: 2 sqmm
Production: 5 specimen, 1994

Projekt:

Research grant entitled: "Reprogrammable neuronlike cell net for specialized imape processing purposes".
Circuit designed in cooperation with Institut of Electronics of TUL.
Funded by Department of Microelectronics and Computer Science.

Chip Details:

Process: Mietec 2.4um CMOS
Area: 9 sqmm
Production: 10 specimen, 1995

Projekt:

"New Methods for Thermal Investigation of Integrated Circuits - (THERMINIC)" - COPERNICUS No.00922.
Research grant entitled: "Modern methods of specialized circuit design – methods of testing and measurements of specialized circuits and systems".

Chip Details:

Process: Mietec 2.4um CMOS
Area: 7 sqmm
Production: 5 specimen, 1995

Projekt:

Joint European Project JEP - 4343 "Education of computer aided design of modern VLSI circuits", 1992-1995.

Chip Details:

Process: Mietec 2.4um CMOS
Area: 2 sqmm
Production: 10 specimen, 1995

CNN-2 - Analog Signal Processor With Neuron-Like Cell Net">

Research grant entitled: "Reprogrammable neuronlike cell net for specialized imape processing purposes".
Circuit designed in cooperation with Institut of Electronics of TUL.
Funded by Department of Microelectronics and Computer Science.

Chip Details:

Process: Mietec 2.4um CMOS
Area: 35.95 sqmm
Production: 10 specimen, 1996

Projekt:

ESPRIT (European Strategic Programme for Research and Development in Information Technology – european contract - CEC-Contract No 8173 - BARMINT (Basic Research for Microsystems Integration)).
The chip contains:
- infrared radiation sensors(IRS)
- electro-thermal converter(ETC)
- gas flow sensors(GFS) which can act also as the ETC device
- acceleration sensor(AS) and punctual light sources(PIX)

Chip Details:

Process: ES2 1.0 MEMS-CMOSDM, SP
Area: 5.95 sqmm
Production: 1996

Projekt:

Structural Joint European Project SJEP-09159 "Postgraduate education in ASIC design".

Chip Details:

Process: VTT 0.8um BiCMOS
Area: 7 sqmm
Production: 5 specimen, 1996

Projekt:

Research grant entitled: "Utilisation of VHDL-A language for computer modelling, design and realisation of integrated microsystems"

Chip Details:

AMS 0.8um CMOS
Area: 11.12 sqmm
Production: 15 specimen, 1999

Projekt:

4-bit analog-digital current-mode converter and transconductance amplifier
Research grant entitled: "Methods of design and realization of analog VLSI circuits for high frequency range"

Chip Details:

AMS 0.8um CMOS
Area: 5 sqmm
Production: 1999

Projekt:

The work supported by the grant of State Committee for Scientific Research No. 8 T11B 021 19 and partly by University Internal Grant No. K-25/Dz.St./1/2001.
X, Y and Z-axis capacitive acceleration sensors, fabricated using a surface micromachining technology.

Chip details:

Process: polyMUMPS
Area: 25 sqmm
Production: 4 specimen, France 2003

Projekt:

An ASIC containing a set of switched-current (SI) circuits.
Its main part comprises several low-pass Tchebyshev filters which realize identical transfer functions using different topologies and a number of functional switched-current blocks: integrator, differentiator, delay element and several distinctive memory cells.

Chip Details:

Process: AMS 0.8um CYE AMS
Area: 10 sqmm
Production: 10 specimen, Belgium 2002

Projekt:

Project related to PhD study research: "Simulation and design of integrated analog-digital Sigma-Delta converters for silicon microsystems applications".
It contains of modular structure of sigma-delta converter and PTAT temperature sensor. It is possible to adjust from 1st to 4th order sigma-delta modulator.

Chip details:

Process: AMS 0.6um CMOS
Area: 4.2 sqmm
Production: 20 specimen, Germany 2003

Projekt:

Research grant entitled: "Analog-digital speech-recognition system for multimedia systems."

Chip details:

Process: AMS CSI 0.35um CMOS
Area: 10 sqmm
Production: 2004

Projekt:

V EUROPEAN PROJECT IST-2000-30193 REASON - Research and Training Action for System on Chip Design

Chip Details:

Process: AMS 0.35um CMOS
Area: 10 sqmm
Production: 20 specimen, 2004

Projekt:

Co-design of mixed-signal high-voltage ASIC for automotive applications.

Chip Details:

Process: 0.8um SOI
Area: -
Production: in production

Projekt:

Design of mixed-signal high-voltage ASIC for automotive applications.

Chip Details:

Process: 0.8um SOI
Area: -
Production: tests

Projekt:

PERPLEXUS (Pervasive computing framework for modeling complex virtually-unbounded systems - VI FP, Contract Number 034632). The chip contains 4x4 array of configurable blocks. Its is a prototype of dynamically reconfigurable FPGA supporting self-replication and auto-routing mechanisms. Configurable blocks contain also small ALUs, thus the chip can work as a multi-core processor.

Chip Details:

Process: UMC 180 nm CMOS
Area: 25 sqmm
Production: 2008

Projekt:

PERPLEXUS (Pervasive computing framework for modeling complex virtually-unbounded systems - VI FP, Contract Number 034632). The chip contains 10x10 array of configurable blocks. Its is a prototype of dynamically reconfigurable FPGA supporting self-replication and auto-routing mechanisms. Configurable blocks contain also small ALUs, thus the chip can work as a multi-core processor.

Chip Details:

Process: UMC 180 nm CMOS
Area: 50 sqmm
Production: 2009